Extended State-Based OSG Configurations for SOGI PLL With an Enhanced Disturbance Rejection Capability
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, New York University, Brooklyn, NY, USA
2. Advanced Power and Energy Center, Electrical Engineering and Computer Science Department, Khalifa University, Abu Dhabi, United Arab Emirates
Funder
Khalifa University Competitive Internal Research Award
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Control and Systems Engineering
Link
http://xplorestaging.ieee.org/ielx7/28/9956958/09847341.pdf?arnumber=9847341
Reference27 articles.
1. Design of a high-performance high-pass generalized integrator based single-phase PLL;kulkarni;J Power Electron,2017
2. Robust frequency‐locked loop algorithm for grid synchronisation of single‐phase applications under distorted grid conditions
3. Addressing DC Component in PLL and Notch Filter Algorithms
4. Design of a fast response time single-phase PLL with dc offset rejection capability
5. Reduced-Order Generalized Integrator-Based Phase-Locked Loop: Performance Improvement for Grid Synchronization of Single-Phase Inverters
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