Development of Interface Model and Design of Compensator to Overcome Delay Response in a PHIL Setup for Evaluating a Grid-Connected Power Electronic DUT-Reference-Cited by-同舟云学术

Development of Interface Model and Design of Compensator to Overcome Delay Response in a PHIL Setup for Evaluating a Grid-Connected Power Electronic DUT

Published:2022-05 Issue:3 Volume:58 Page:4109-4121
ISSN:0093-9994
Container-title:IEEE Transactions on Industry Applications
language:
Short-container-title:IEEE Trans. on Ind. Applicat.

Author:

Pokharel Mandip¹^ORCID,Ho Carl Ngai Man¹^ORCID

Affiliation:

1. RIGA Laboratory, Department of Electrical and Computer Engineering, University of Manitoba, Winnipeg, MB, Canada

Funder

Natural Sciences and Engineering Research Council of Canada

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Control and Systems Engineering

Link

http://xplorestaging.ieee.org/ielx7/28/9778222/09735272.pdf?arnumber=9735272

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4. Control Issues in Systems with Loop Delays

5. Power Hardware-in-the-Loop-Based Anti-Islanding Evaluation and Demonstration

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