A 10-bit high speed pipelined ADC

Author:

Murshed Alfakhri M.,Krishna K. Lokesh,Saif M. Abdullah,Anuradha K.

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Analysis of CMOS Full Adder Circuits for Multiplier Logic Architectures;2024 International Conference on Distributed Computing and Optimization Techniques (ICDCOT);2024-03-15

2. An Energy Efficient High-Performance CMOS Transmission Gate Full Adder Circuit;2023 International Conference on Sustainable Computing and Data Communication Systems (ICSCDS);2023-03-23

3. Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches;Circuits, Systems, and Signal Processing;2021-02-13

4. An 8-Bit Charge Redistribution SAR ADC;Intelligent Computing Techniques for Smart Energy Systems;2019-12-17

5. Analysis and Simulation of Single Tail and Double Tail Circuits;2019 4th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT);2019-12

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