Low Jitter and Low Power PLL：Towards The Utopia
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low Noise and Spur Sub-sampling Phase Locked Loop Based on Clock System;2023 6th World Conference on Computing and Communication Technologies (WCCCT);2023-01-06
2. 10GHz Low Current Mismatch Pseudo-Differential Charge Pump Phase-Locked Loop Circuit Design;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28