Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators-Reference-Cited by-同舟云学术

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Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators

Published:2019-09 Issue:3 Volume:11 Page:69-72
ISSN:1943-0663
Container-title:IEEE Embedded Systems Letters
language:
Short-container-title:IEEE Embedded Syst. Lett.

Author:

Rubattu Claudio^ORCID,Palumbo Francesca^ORCID,Sau Carlo^ORCID,Salvador Ruben^ORCID,Serot Jocelyn,Desnos Karol,Raffo Luigi,Pelcat Maxime

Funder

H2020 LEIT Information and Communication Technologies

PROSSIMO Project

HiPEAC Project (H2020)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Computer Science,Control and Systems Engineering

Link

http://xplorestaging.ieee.org/ielx7/4563995/8818469/08543666.pdf?arnumber=8543666

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. FPGA-based Implementation for Industrial Motion Control System;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27

2. An Automated Design Flow for Adaptive Neural Network Hardware Accelerators;Journal of Signal Processing Systems;2023-04-26

3. The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design;Microprocessors and Microsystems;2021-02

4. Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators;Electronics;2021-01-03

5. ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs;2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2020-07

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