2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR-Reference-Cited by-同舟云学术

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2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR

Published:2010-05 Issue: Volume: Page:
ISSN:
Container-title:2010 IEEE Radio Frequency Integrated Circuits Symposium
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Author:

Mazouffre O.,Toupe R.,Pignol M.,Deval Y.,Begueret J.B.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5472210/5477245/05477391.pdf?arnumber=5477391

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Injection-Locked Ring Oscillator based Phase-Lacked-Loop for 1.6 Gbps Clock Recovery;2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2021-08-23

2. A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS;2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2021-06-07

3. A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link;IEICE Transactions on Electronics;2016

4. SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link;IEEE Journal of Solid-State Circuits;2014-09

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