On the Compensation of Timing Mismatch in Two-Channel Time-Interleaved ADCs: Strategies and a Novel Parallel Compensation Structure

Author:

Wang Yinan1ORCID,Johansson Hakan2ORCID,Deng Mingxin1,Li Zhiwei1ORCID

Affiliation:

1. College of Electronic Science and Technology, National University of Defense Technology, Changsha, China

2. Division of Communication Systems, Department of Electrical Engineering, Linköping University, Linköping, Sweden

Funder

National Natural Science Foundation of China

Science and Technology on Analog Integrated Circuit Laboratory

National University of Defense and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Signal Processing

Reference39 articles.

1. Digital Signal Processing with Field Programmable Gate Arrays

2. TI-ADCs SFDR requirement analysis

3. A method to improve SFDR with random interleaved sampling method

4. A 90 dB-SFDR 14b 500 MS/s BiCMOS switched-current pipelined ADC;el-chammas;Proc IEEE Int Solid-State Circuits Conf,0

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