Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Instrumentation
Cited by
4 articles.
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1. A nonuniform DPLL architecture for optimized performance;IEEJ Transactions on Electrical and Electronic Engineering;2013-11-26
2. Improved First-Order Time-Delay Tanlock Loop Architectures;IEEE Transactions on Circuits and Systems I: Regular Papers;2006-09
3. Design-for-testability for embedded delay-locked loops;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-08
4. Design for Testability in PLLs;Clock Generators for SOC Processors