A Duty Cycle Error Reduction with 1-point Calibration achieving 0.017UI in 7.2Gbps HBM3 DRAM Data Read
Author:
Affiliation:
1. Intel,Bengaluru,Karnataka,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9907764/9908069/09908129.pdf?arnumber=9908129
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1. Differential multi-phase DLL for reconfigurable radio frequency synthesizer
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4. 23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme
5. A 12.8-Gb/s Quarter-Rate Transmitter Using a 4:1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner
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