Exact and Heuristic Algorithms for a bi-criteria Order-Lot Pegging Problem in a Multi-Fab Setting
Author:
Affiliation:
1. University of Hagen,Department of Mathematics and Computer Science,Hagen,Germany,58097
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10406299/10407113/10407942.pdf?arnumber=10407942
Reference27 articles.
1. A Due-date Based Algorithm for Order-lot Pegging in a Semiconductor Wafer Fabrication Facility;Bang
2. Genetic Algorithms and Random Keys for Sequencing and Optimization
3. Evaluation of heuristics for a class-constrained lot-to-order matching problem in semiconductor manufacturing
4. Bin covering algorithms in the second stage of the lot to order matching problem
5. Modelling and analysis of semiconductor manufacturing in a shrinking world: challenges and successes
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