Real time implementation of Vector Delay Lock Loop on a GNSS receiver hardware with an open software interface
Author:
Affiliation:
1. Fraunhofer Institute for Integrated Circuits (IIS), Nuremberg, Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8710211/8714121/08714175.pdf?arnumber=8714175
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Quad-Band Multi-Constellation Global Navigation Satellite System Receiver Development Platform with System-on-Chip Architecture;ENC 2023;2023-10-29
2. Characteristics of the IGS receiver clock performance from multi-GNSS PPP solutions;GPS Solutions;2023-01
3. Evaluation of Adaptive Loop-Bandwidth Tracking Techniques in GNSS Receivers;Sensors;2021-01-12
4. Frequency Diversity Combined Robust GNSS Signal Tracking Using a Bank of Correlators;Proceedings of the 33rd International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2020);2020-10-28
5. Real Time Results of Vector Delay Lock Loop in a Light Urban Scenario;2020 IEEE/ION Position, Location and Navigation Symposium (PLANS);2020-04
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