Author:
Nagaraj S.,Thyagarajan K.,Srihari D.,Gopi K.
Cited by
5 articles.
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1. Hardware Implementation of the Multiplier Using Argument Bit Grouping;2024 XXVII International Conference on Soft Computing and Measurements (SCM);2024-05-22
2. A Comparative Analysis of Switched Gate Implementations in Wallace Tree Multipliers;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03
3. Design and Implementation of 8-Bit Vedic Multiplier Using Cadence 45nm Technology;2024 Fourth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT);2024-01-11
4. Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders;2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT);2022-10-03
5. Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata;Materials Today: Proceedings;2021