Implementation of Low-Power Frequency Divider Circuit using GDI Technique

Author:

Pandey Priyanka1,Kumar Amit1,Singh Rajiv Kumar1

Affiliation:

1. Institute of Engg. & Tech. Lucknow Dr APJ AKTU,Dept. of Electronics & Comm Engg.,Lucknow,India,226021

Publisher

IEEE

Reference20 articles.

1. An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop

2. Low power, high speed hybrid clock divider circuit

3. Design & analysis of modified conditional data mapping flip-flop to ultra low power and high-speed applications;singh;Int J Sci Res,2014

4. High-performance and low power conditional discharge flip-flop;bayoumi;IEEE Trans VLSI Syst,2004

5. Design and simulation of frequency divider circuit based on multisim

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Analysis of a FinFET Based Multiplexers for Ultra Low Power Applications using GDI Technique;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14

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