A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability-Reference-Cited by-同舟云学术

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A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability

Published:2019-10 Issue:10 Volume:2 Page:223-226
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Truesdell Daniel S.^ORCID,Dissanayake Anjana,Calhoun Benton H.

Funder

NSF NERC ASSIST Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/8011414/8887430/8863976-aam.pdf

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 254-nW 20-kHz On-Chip RC Oscillator With 21-ppm/°C Minimum Temperature Stability and 10-ppm Long Term Stability;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

2. Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-02

3. RC Frequency References Based on Dual RC FLLs;Biomedical Electronics, Noise Shaping ADCs, and Frequency References;2023

4. A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer;2022 19th International SoC Design Conference (ISOCC);2022-10-19

5. A Frequency-Locked Oscillator Using Complex RC Impedance IQ-Balancing;IEEE Journal of Solid-State Circuits;2022-03

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