Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL-Reference-Cited by-同舟云学术

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL

Published:2019-12 Issue:12 Volume:2 Page:289-292
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Rovinski Austin^ORCID,Veluri Bandhav,Rao Anuj,Ajayi Tutu,Puscar Julian,Dai Steve,Zhao Ritchie,Richmond Dustin,Zhang Zhiru,Galton Ian,Batten Christopher,Zhao Chun,Taylor Michael B.,Dreslinski Ronald G.,Al-Hawaj Khalid,Gao Paul,Xie Shaolin,Torng Christopher,Davidson Scott,Amarnath Aporva,Vega Luis

Funder

Defense Advanced Research Projects Agency

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/8011414/8939156/8903494-aam.pdf

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