Impact of Co-Integration on the Performance of Full CMOS Based Hybrid SET-FET Circuits for Scalable Quantum Computing using FinFET Technologies-Reference-Cited by-同舟云学术

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Impact of Co-Integration on the Performance of Full CMOS Based Hybrid SET-FET Circuits for Scalable Quantum Computing using FinFET Technologies

Published:2024-03-03 Issue: Volume: Page:1-3
ISSN:
Container-title:2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
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Author:

Singh Sujit Kumar¹,Sharma Deepesh¹,Srinivasan P.²,Dixit Abhisek¹

Affiliation:

1. IIT,Delhi,India

2. GLOBALFOUNDRIES,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10511270/10511310/10511467.pdf?arnumber=10511467

Reference8 articles.

1. Quantum Computing in the NISQ era and beyond

2. A cryogenic CMOS chip for generating control signals for multiple qubits

3. High Volume Electrical Characterization of Semiconductor Qubits

4. Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model

5. Compact Model of a Bulk FinFET Quantum Dot Toward Single Chip Integration of Qubits and Control Electronics for Quantum Computing Applications

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance Analysis and Compact Modeling of 12-nm P-channel Bulk FinFETs at Cryogenic Operating Temperatures for Quantum Computing Applications;2024 IEEE Latin American Electron Devices Conference (LAEDC);2024-05-08

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