Microarchitecture and Design of a Watchdog Timer for aRISC-V based SoC
Author:
Affiliation:
1. Vidyavardhaka College of Engineering,Dept. of Electronics and Communication Engineering,Mysuru,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10099475/10099489/10099615.pdf?arnumber=10099615
Reference15 articles.
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3. Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs
4. FPGA implementation of multiple hardware watchdog timers for enhancing real-time systems security
5. RTL implementation for AMBA ASB APB protocol at system on chip level
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