Accuracy and speed-up of parallel trace-driven architectural simulation-Reference-Cited by-同舟云学术

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Accuracy and speed-up of parallel trace-driven architectural simulation

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Container-title:Proceedings 11th International Parallel Processing Symposium
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Author:

Nguyen A.-T.,Bose P.,Ekanadham K.,Nanda A.,Michael M.

Publisher

IEEE Comput. Soc. Press

Link

http://xplorestaging.ieee.org/ielx3/4440/12600/00580842.pdf?arnumber=580842

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation;2023 IEEE/ACM 27th International Symposium on Distributed Simulation and Real Time Applications (DS-RT);2023-10-04

2. Fast, accurate, and scalable memory modeling of GPGPUs using reuse profiles;Proceedings of the 34th ACM International Conference on Supercomputing;2020-06-29

3. A Scalable Analytical Memory Model for CPU Performance Prediction;Lecture Notes in Computer Science;2017-12-23

4. Using the first-level cache stack distance histograms to predict multi-level LRU cache misses;Microprocessors and Microsystems;2017-11

5. Computer Architecture Performance Evaluation Methods;Synthesis Lectures on Computer Architecture;2010-12-22

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