Memory hierarchy management for iterative graph structures
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx4/5485/14764/00669929.pdf?arnumber=669929
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Spatiotemporal Graph and Hypergraph Partitioning Models for Sparse Matrix-Vector Multiplication on Many-Core Architectures;IEEE Transactions on Parallel and Distributed Systems;2019-02-01
2. Impact of Traditional Sparse Optimizations on a Migratory Thread Architecture;2018 IEEE/ACM 8th Workshop on Irregular Applications: Architectures and Algorithms (IA3);2018-11
3. An approach for code generation in the Sparse Polyhedral Framework;Parallel Computing;2016-04
4. A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs;IEEE Transactions on Computers;2015-04
5. Hypergraph Partitioning Based Models and Methods for Exploiting Cache Locality in Sparse Matrix-Vector Multiplication;SIAM Journal on Scientific Computing;2013-01
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