A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction

Author:

Li Xiaoling1,Chen Hao1,Paul Riya1,Mukherjee Shilpi1,Du Xia1,Cuzner Robert2,Song Xiaoqing1,Zhao Yue1,Mantooth H. Alan1

Affiliation:

1. University of Arkansas,Department of Electrical Engineering,Fayetteville,AR,USA

2. College of Engineering and Applied Science, University of Wisconsin-Milwaukee,Milwaukee,WI,USA

Funder

National Science Foundation

Publisher

IEEE

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 10 kV SiC MOSFET Power Module With Optimized System Interface and Electric Field Distribution;IEEE Transactions on Power Electronics;2024-08

2. A Review of Partial Discharge in Medium Voltage SiC Power Modules Under Square Wave Excitation: Characterization, Mitigation, and Detection;IEEE Journal of Emerging and Selected Topics in Power Electronics;2024-08

3. Application and Benefit Analysis of Guard Ring Methods in Reducing the Maximum Electric Field of Half Bridge Power Module;2024 IEEE 10th International Power Electronics and Motion Control Conference (IPEMC2024-ECCE Asia);2024-05-17

4. Electric Field Optimization for Enhanced Insulation in 10kV SiC MOSFET Power Modules Based on Chipwall Integration;2024 IEEE 7th International Electrical and Energy Conference (CIEEC);2024-05-10

5. Methods for increasing the Partial Discharge Inception Voltage of Power Module Substrates using Guard Ring Structures;2024 IEEE Applied Power Electronics Conference and Exposition (APEC);2024-02-25

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