Low Power and Less Delay Circuit Shared Static Flip-Flop (LDCSSFF) for Digital Applications-Reference-Cited by-同舟云学术

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Low Power and Less Delay Circuit Shared Static Flip-Flop (LDCSSFF) for Digital Applications

Published:2021-11-27 Issue: Volume: Page:
ISSN:
Container-title:2021 Innovations in Power and Advanced Computing Technologies (i-PACT)
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Author:

Jogi Prakash¹,Karanam Rajini²,Ravi Kishore G³,Biroju Ravikiran¹,Akula Rajini¹,Kunsoth Umarani¹

Affiliation:

1. Sree Dattha Group of Institutions,Electronics and Communication Engineering,Hyderabad,India

2. KG Reddy College of Engineering and Technology,Electronics and Communication Engineering,Hyderabad,India

3. Vidya Jyothi Institute of Technology,Electronics and Communication Engineering,Hyderabad,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9696358/9696444/09696452.pdf?arnumber=9696452

Reference19 articles.

1. Study and analysis of universal gates using stacking low power technique;goyal;International Journal of Computer Science and Information Technologies,2014

2. 12.7-times energy efficiency increase of 16-bit integer unit by power suppy voltage(VDD) scaling from 1.2v to 310mV enabled by contention less flip flops(CLFF) and separated VDD between flip flops and combinational logics;fuketa;Int Symp Low Power Electronics and Design (ISLPED),0

3. A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

4. ultra-low voltage, Minimum energy CMOS;hanson;IBM J Res&Dev,2006

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