Simulation and Performance Analysis of Hetero Dielectric Underlap Asymmetrical Double-Gate MOSFET Using Gate Stack
Author:
Affiliation:
1. National Institute of Technology,Department of Electronics and Communication Engineering,Warangal,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9691480/9691481/09691765.pdf?arnumber=9691765
Reference21 articles.
1. Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors
2. Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs
3. Analysis of high-K spacer asymmetric underlap DG-MOSFET for SOC application;koley;IEEE Trans Electron Devices,2015
4. Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length
5. Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications
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