An Efficient Low-Power VIP-based VC Router Architecture for Mesh-based NoC
Author:
Affiliation:
1. National Institute of Technology Tiruchirappalli,Department of Electronics and Communication Engineering,India
2. VNR Vignana Jyothi Institute of Engineering and Technology,Department of ECE,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10038981/10039721/10040017.pdf?arnumber=10040017
Reference12 articles.
1. A highly efficient dynamic router for application-oriented network on chip
2. Virtual Point-to-Point Connections for NoCs
3. BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass
4. An encapsulated packet-selection routing for network on chip
5. A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core
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