C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations-Reference-Cited by-同舟云学术

C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations

Published:2022-05-28 Issue: Volume: Page:
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Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

He Yifan¹,Huang Yuxuan¹,Yue Jinshan¹,Sun Wenyu¹,Zhang Lu¹,Liu Yongpan¹

Affiliation:

1. Tsinghua University,Dept. of Electronic Engineering,Beijing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937513.pdf?arnumber=9937513

Reference20 articles.

1. A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

2. A 14nm 100kb 2t1r transpose rram with >50× resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme;wang;2021 Symposia on VLSI Technology and Circuits,2021

3. A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

4. 24.1 A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors

5. 15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices

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1. A CMOS Analog Neuron Circuit with A Multi-Level Memory;2023 International Conference on Microelectronics (ICM);2023-12-17

2. Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

4. A Multilayer Neural Accelerator With Binary Activations Based on Phase-Change Memory;IEEE Transactions on Electron Devices;2023-03