A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC
Author:
Affiliation:
1. University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST,Macao,China
2. Shanghai Jiao Tong University,Department of Micro-Nano Electronics,Shanghai,China
3. Amicro Semiconductor Co., Ltd.,Zhuhai,China
Funder
Technology Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937224.pdf?arnumber=9937224
Reference14 articles.
1. A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
2. A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC
3. A 0.46 mW 5 MHz-BW 79.7 dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter;liu;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech,2017
4. A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators;guo;Proc IEEE Symp VLSI Circuits,2017
5. A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme;International Journal of Circuit Theory and Applications;2024-06-18
2. Stability analysis and optimization of CT DSMs with an NS SAR quantizer by a redistributed noise shaping technique;Microelectronics Journal;2024-06
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