A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC

Author:

Li Ke1,Sin Sai-Weng1,Qi Liang2,Zhao Weibing3,Wang Guoxing2,Martins R.P.1

Affiliation:

1. University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST,Macao,China

2. Shanghai Jiao Tong University,Department of Micro-Nano Electronics,Shanghai,China

3. Amicro Semiconductor Co., Ltd.,Zhuhai,China

Funder

Technology Development

Publisher

IEEE

Reference14 articles.

1. A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

2. A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

3. A 0.46 mW 5 MHz-BW 79.7 dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter;liu;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech,2017

4. A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators;guo;Proc IEEE Symp VLSI Circuits,2017

5. A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

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