DRAM Bitline as A Delay Path for Potential PUF
Author:
Affiliation:
1. Khalifa University,System on Chip Lab (SoC),Department of Electrical and Computer Engineering,Abu Dhabi,UAE
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10378847/10378878/10378924.pdf?arnumber=10378924
Reference14 articles.
1. Analysis and Evaluation of PUF-Based SoC Designs for Security Applications
2. A PUF-based paradigm for IoT security
3. Extraction of Device Fingerprints Using Built-in Erase-Suspend Operation of Flash Memory Devices
4. A DRAM based physical unclonable function capable of generating >1032 Challenge Response Pairs per 1Kbit array for secure chip authentication
5. The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
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