Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning
Author:
Das P.,Gupta S. K.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Path Unselection for Path Delay Fault Test Generation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
2. Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines;2022 IEEE 31st Asian Test Symposium (ATS);2022-11
3. Introduction;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018
4. Speed Binning Using Machine Learning And On-chip Slack Sensors;Proceedings of the 25th edition on Great Lakes Symposium on VLSI;2015-05-20