Spatial retardation of carrier heating in scaled 0.1-μm n-MOSFET's using Monte Carlo simulations-Reference-Cited by-同舟云学术

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Spatial retardation of carrier heating in scaled 0.1-μm n-MOSFET's using Monte Carlo simulations

Published:1996-04 Issue:4 Volume:43 Page:661-663
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Hulfachor R.B.,Ellis-Monaghan J.J.,Kim K.W.,Littlejohn M.A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/10358/00485550.pdf?arnumber=485550

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis of hot-electron reliability and device performance in 80-nm double-gate SOI n-MOSFET's;IEEE Transactions on Electron Devices;1999

2. Scaling trends for device performance and reliability in channel-engineered n-MOSFETs;IEEE Transactions on Electron Devices;1998

3. Role of e-e scattering in the enhancement of channel hot carrier degradation of deep sub-micron NMOSFETs at high V/sub GS/ conditions;2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167)

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