Author:
Lee Tsung-Hsien,Wang Ting-Chi
Cited by
8 articles.
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1. A Survey on Steiner Tree Construction and Global Routing for VLSI Design;IEEE Access;2020
2. TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-01
3. Incremental Layer Assignment for Timing Optimization;ACM Transactions on Design Automation of Electronic Systems;2017-07-22
4. Nanowire-Aware Routing Considering High Cut Mask Complexity;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-06
5. Incremental layer assignment for critical path timing;Proceedings of the 53rd Annual Design Automation Conference;2016-06-05