Design of ESD Protection Circuits for LNA Using 65-nm CMOS Technology
Author:
Affiliation:
1. Amrita School of Engineering, Amrita Vishwa Vidyapeetham,Department of Electronics and Communication Engineering,Coimbatore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9707903/9708074/09708297.pdf?arnumber=9708297
Reference17 articles.
1. Design of LNA using body biasing techniques for enhanced reliabilty and robustness;karthigha;2018 3rd International Conference on Communication and Electronics Systems (ICCES) ICCES,2018
2. A variable gain 2.4-GHz CMOS low noise amplifier employing body biasing
3. Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio
4. Model and Analysis of Planar Spiral Inductor Based on Package Substrate
5. Direct Coupled Spiral Resonator for Band Stop Filter Applications
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