Study of parametric variations on Heterojunction Dual Gate Vertical TFET for performance Enhancement
Author:
Affiliation:
1. National Institute of Technology,Department of Electronics and Communication Engineering,Silchar,Assam,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10404094/10404112/10405010.pdf?arnumber=10405010
Reference20 articles.
1. Design and Parametric Analysis of Charge Plasma Junctionless TFET for Biosensor Applications
2. Extended Gate to source overlap Heterojunction Vertical TFET: Design, analysis, and optimization with process parameter variations
3. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric
4. Tunnel Field-Effect Transistors: State-of-the-Art
5. Demonstration of L-Shaped Tunnel Field-Effect Transistors
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