Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation-Reference-Cited by-同舟云学术

Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation

Published:2022-12 Issue:12 Volume:69 Page:5072-5084
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Osada Masaru¹^ORCID,Xu Zule²^ORCID,Shibata Ryoya¹,Iizuka Tetsuya²^ORCID

Affiliation:

1. Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan

2. Systems Design Laboratory, School of Engineering, The University of Tokyo, Tokyo, Japan

Funder

Institute for AI and Beyond

The University of Tokyo

Japan Society for the Promotion of Science (JSPS) KAKENHI

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/9985434/09899485.pdf?arnumber=9899485

Reference21 articles.

1. A 3.2-to-3.8 GHz calibration-free harmonic-mixer-based dual-feedback fractional-N PLL achieving ?66 dBc worst-case in-band fractional spur;osada;Proc IEEE Symp VLSI Circuits,2020

2. An FBAR driven ?261dB FOM fractional-N PLL;yang;Proc IEEE Radio Freq Integr Circuits Symp (RFIC),2021

3. A sub-100 MHz reference-driven 25-to-28 GHz fractional-N PLL with ?250 dB FoM;yang;Proc IEEE Int Solid-State Circuits Conf (ISSCC),2022

4. An Alternative Analysis of Noise Folding in Fractional-N Synthesizers

5. Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers

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1. A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering;IEEE Journal of Solid-State Circuits;2024-07