A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs-Reference-Cited by-同舟云学术

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A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs

Published:2023-05 Issue:5 Volume:70 Page:2003-2015
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Gao Zhen¹^ORCID,Xiao Jiajun¹,Liu Qiang²^ORCID,Ullah Anees³^ORCID,Reviriego Pedro⁴^ORCID

Affiliation:

1. School of Electrical and Information Engineering, Tianjin University, Tianjin, China

2. School of Microelectronics, Tianjin University, Tianjin, China

3. Department of Electronics Engineering, University of Engineering and Technology, Peshawar, Abbottabad, Pakistan

4. Departamento de Ingenería de Sistemas Telemáticos, Universidad Politécnica de Madrid, Madrid, Spain

Funder

National Natural Science Foundation of China

ACHILLES

Go2Edge Network

Ministerio de Ciencia y Tecnología

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10109891/10025839.pdf?arnumber=10025839

Reference43 articles.

1. Algorithm-based fault tolerance for FFT networks

2. Polyphase Channelizer Demystified [Lecture Notes]

3. Fault Tolerant Polyphase Filters-based Decimators for SRAM-based FPGA Implementations

4. A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

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