A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences

Author:

Karimzadeh ForoozanORCID,Cao NingyuanORCID,Crafton BrianORCID,Romberg JustinORCID,Raychowdhury ArijitORCID

Funder

Semiconductor Research Corporation under Grant Joint University Microelectronics Program (JUMP) Center for Brain-inspired Computing Enabling Autonomous Intelligence

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. 64-Bit High Speed Counter with Galois LFSR;2024 International Conference on Circuit, Systems and Communication (ICCSC);2024-06-28

2. Twofold Sparsity: Joint Bit- and Network-Level Sparsity for Energy-Efficient Deep Neural Network Using RRAM Based Compute-In-Memory;IEEE Access;2024

3. Design and Analysis of Non-vulnerable PRBS Generation with Internal Shift and XOR of LFSR;Lecture Notes in Electrical Engineering;2024

4. Compressing fully connected layers of deep neural networks using permuted features;IET Computers & Digital Techniques;2023-06-11

5. Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

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