Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard
Author:
Affiliation:
1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea
Funder
National Research Foundation of Korea
Ministry of Science and ICT, South Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9763566/09714891.pdf?arnumber=9714891
Reference25 articles.
1. A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes
2. High-throughput layered decoder implementation for quasi-cyclic LDPC codes
3. A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications
4. High-Speed LDPC Decoders Towards 1 Tb/s
5. A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard
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3. Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-06
4. A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-06
5. Channel Coding Toward 6G: Technical Overview and Outlook;IEEE Open Journal of the Communications Society;2024
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