Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/I DS Methodology-Reference-Cited by-同舟云学术

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Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/I DS Methodology

Published:2021-02 Issue:2 Volume:68 Page:631-640
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Tajalli Armin^ORCID

Funder

University of Utah and Kandou Bus, Switzerland

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9325891/09261456.pdf?arnumber=9261456

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

2. Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using $\mathrm{C}/\mathrm{I}_{\mathrm{D}}$ Methodology;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27

3. Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET;Nanotechnology;2023-12-19

4. Opportunities and Challenges in Agri-Food Systems Enabled by Advance in Electronics;2023 International Conference on Sustainable Technology and Engineering (i-COSTE);2023-12-04

5. Multistage Op Amp design space exploration by gm/ID$$ {g}_m/{I}_D $$ sampling and symbolic design equations;International Journal of Circuit Theory and Applications;2023-09-25

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