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Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs

  • Published:2022-02 Issue:2 Volume:69 Page:707-720
  • ISSN:1549-8328
  • Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Yang JeonggyuORCID,Lee HyundongORCID,Jeong Jae HoonORCID,Kim TaehakORCID,Lee Sin-HyungORCID,Song TaigonORCID

Funder

National Research and Development Program through the National Research Foundation of Korea

Ministry of Science and ICT

National Research Foundation of Korea

Korean Government

BrainKorea21 FOUR (BK21 FOUR) Project by the Ministry of Education, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 27 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low power and energy efficient design of ternary D-latch based on CNTFET-RRAM technology;International Journal of Information Technology;2024-08-28

2. A Complementary Resistive Switch-Based Balanced Ternary Logic;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18

3. Crossbar array based on tri-valued memristors: its design and application;Nonlinear Dynamics;2024-08-12

4. Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-05

5. Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology;International Journal of Circuit Theory and Applications;2024-03-21
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