Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication

Author:

Liu YaoORCID,Zhang JunyiORCID,Liu ShuoORCID,Wang Qiaoling,Dai WangchenORCID,Cheung Ray Chak ChungORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. When In-Network Computing Meets Distributed Machine Learning;IEEE Network;2024-09

2. OmNICCL: Zero-cost Sparse AllReduce with Direct Cache Access and SmartNICs;Proceedings of the 2024 SIGCOMM Workshop on Networks for AI Computing;2024-08-04

3. Host-driven In-Network Aggregation on RDMA;IEEE INFOCOM 2024 - IEEE Conference on Computer Communications;2024-05-20

4. Distributed Analytics For Big Data: A Survey;Neurocomputing;2024-03

5. GPU-Efficient Deployment of Ring All-Reduce-Based Distributed Model Training in Tidal Computing Power Network;2023 Asia Communications and Photonics Conference/2023 International Photonics and Optoelectronics Meetings (ACP/POEM);2023-11-04

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