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Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers

  • Published:2021-02 Issue:2 Volume:68 Page:715-727
  • ISSN:1549-8328
  • Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Lyu FeiORCID,Xu Xiaoqi,Wang Yu,Luo YuanyongORCID,Wang YuxuanORCID,Pan HongbingORCID

Funder

Scientific Research Foundation for the High-Level Talents of Jinling Institute of Technology

Natural Science Foundation of the Jiangsu Higher Education Institutions of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analysis of Pruned Approximate Majority Logic Based Adder;2023 Second International Conference on Advances in Computational Intelligence and Communication (ICACIC);2023-12-07

2. High-Precision Method and Architecture for Base-2 Softmax Function in DNN Training;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-08

3. A New Angle Set-Based Absolute Scaling-free Reconfigurable Cordic Algorithm;Circuits, Systems, and Signal Processing;2023-07-23

4. An Efficient Hardware Implementation for Complex Square Root Calculation Using a PWL Method;Electronics;2023-07-09

5. Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
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