Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic-Reference-Cited by-同舟云学术

Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic

Published:2022-06 Issue:6 Volume:69 Page:2423-2434
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wang Xiao-Yuan¹^ORCID,Dong Chuan-Tao¹,Zhou Peng-Fei¹,Nandi Sanjoy Kumar²^ORCID,Nath Shimul Kanti²^ORCID,Elliman Robert G.²^ORCID,Iu Herbert Ho-Ching³^ORCID,Kang Sung-Mo⁴,Eshraghian Jason K.⁵^ORCID

Affiliation:

1. School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, China

2. Department of Materials Physics, Research School of Physics, The Australian National University, Canberra, ACT, Australia

3. School of Electrical and Electronic Engineering, The University of Western Australia, Crawley, WA, Australia

4. Department of Electrical and Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA

5. College of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA

Funder

National Natural Science Foundation of China

Natural Science Foundation of Zhejiang Province

Australian Research Council (ARC) and Varian Semiconductor Equipment/Applied Materials

ARC Linkage Project

Forrest Research Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/9782465/09724615.pdf?arnumber=9724615

Reference49 articles.

1. A novel CNTFET-based ternary logic gate design

2. The generalized metastable switch memristor model;molter;Proc 15th Int Workshop Cellular Nanosc Netw Appl (CNNA),2016

3. Memristor based unbalanced ternary logic gates

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