An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain–Computer Interface SoCs-Reference-Cited by-同舟云学术

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An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain–Computer Interface SoCs

Published:2022-12 Issue:12 Volume:69 Page:4872-4885
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Byun Wooseok¹^ORCID,Je Minkyu²^ORCID,Kim Ji-Hoon³^ORCID

Affiliation:

1. Architecture Team, SAPEON Korea Inc., Seongnam, South Korea

2. School of Electrical Engineering, KAIST, Daejeon, South Korea

3. Department of Electronic and Electrical Engineering, Smart Factory Multidisciplinary Program, Ewha Womans University, Seoul, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/9985434/09857640.pdf?arnumber=9857640

Reference43 articles.

1. Inversion of Matrices by Biorthogonalization and Related Results

2. Spectral decomposition via systolic triarray based on QR iteration

3. Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection

4. BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge

5. TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

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2. Algorithm-Hardware Co-Design for Wearable BCIs: An Evolution from Linear Algebra to Transformers;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

4. NASA+: Neural Architecture Search and Acceleration for Multiplication-Reduced Hybrid Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-06

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