A 24–29.5-GHz Scalable 2 $\times$ 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems-Reference-Cited by-同舟云学术

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A 24–29.5-GHz Scalable 2 $\times$ 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems

Published:2024 Issue: Volume: Page:1-14
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wang Long¹^ORCID,Chen Jixin¹^ORCID,Chen Zhe¹^ORCID,Xia Xiaoyue²^ORCID,Hu Yun³^ORCID,Zheng Sidou¹^ORCID,Li Zekun¹^ORCID,Zhou Rui¹^ORCID,Zhou Peigen¹^ORCID,Zhou Jianyi¹^ORCID,Hong Wei¹^ORCID

Affiliation:

1. State Key Laboratory of Millimeter Waves, Southeast University, Nanjing, China

2. School of Information Science and Engineering, State Key Laboratory of Millimeter Waves, Southeast University, Nanjing, China

3. Purple Mountain Laboratory, Nanjing, China

Funder

National Key Research and Development Program of China

Fundamental Research Funds for the Central Universities

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/8919/4358591/10634528.pdf?arnumber=10634528

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