A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators-Reference-Cited by-同舟云学术

A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators

Published:2021-08 Issue:8 Volume:68 Page:3305-3316
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Lee Eunyoung^ORCID,Han Taeyoung,Seo Donguk^ORCID,Shin Gicheol^ORCID,Kim Jaerok^ORCID,Kim Seonho,Jeong Soyoun,Rhe Johnny,Park Jaehyun,Ko Jong Hwan^ORCID,Lee Yoonmyung^ORCID

Funder

National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT

Samsung Electronics

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9481308/09437302.pdf?arnumber=9437302

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