Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline

Author:

Eni Yossi,Greenberg ShlomoORCID,Ben-Shimol YehudaORCID

Funder

GenPro Consortium within the framework of the Israel Innovation Authority’s MAGNET Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09

2. A Design of Multithreaded RISC-V Processor for Real-Time System;2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW);2023-11-27

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