Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis

Author:

Kwon Hyunjeong,Kim Daeyeon,Kim Young Hwan,Kang Seokhyeong

Funder

National Research Foundation of Korea

Korea government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Efficient Memory Circuits Yield Analysis and Optimization Framework via Meta-Learning;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-05

3. Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28

4. Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

5. SRP-YOLOX: An improved deep convolutional neural network for automated via detection;Microelectronics Reliability;2023-08

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