Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers-Reference-Cited by-同舟云学术

Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers

Published:2023-07 Issue:7 Volume:70 Page:2834-2843
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Li Xiangyu¹^ORCID,Wang Pengjun¹^ORCID,Li Gang¹^ORCID,Zhang Yuejun²^ORCID

Affiliation:

1. College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou, China

2. Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Natural Science Foundation of Ningbo

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10164683/10107665.pdf?arnumber=10107665

Reference35 articles.

1. A Differential Output Interfacing ASIC for Integrated Capacitive Sensors

2. Continuous-time interface for a micromachined capacitive accelerometer with NEA of 4g and bandwidth of 300Hz

3. Measuring and calibrating of the parasitic mismatch in MEMS accelerometer based on harmonic distortion self-test

4. A High-Performance Digital Interface Circuit for a High-Q Micro-Electromechanical System Accelerometer

5. A 0.23 ?g bias instability and 1.6 ?g/Hz1/2 resolution silicon oscillating accelerometer with build-in ?-? frequency-to-digital converter;zhao;Proc IEEE Symp VLSI Circuits (VLSI-Circuits),2016

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