A Control-Bounded Quadrature Leapfrog ADC-Reference-Cited by-同舟云学术

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A Control-Bounded Quadrature Leapfrog ADC

Published:2024-06 Issue:6 Volume:71 Page:2483-2496
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Malmberg Hampus¹^ORCID,Feyling Fredrik²^ORCID,Rosa José M. de la³^ORCID

Affiliation:

1. Department of Information Technology and Electrical Engineering, ETH Zürich, Zürich, Switzerland

2. Department of Electronic Systems, Norwegian University of Science and Technology, Trondheim, Norway

3. Institute of Microelectronics of Seville, IMSE-CNM, CSIC, University of Seville, Seville, Spain

Funder

Ministerio de Ciencia e Innovacion (MCIN)/Agencia Estatal de Investigacion (AEI)/10

European Union European Social Fund (ESF) Investing in your future

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8919/10541300/10449885.pdf?arnumber=10449885

Reference26 articles.

1. A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay

2. A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer

3. 10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer

4. LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency

5. A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR$ =$ 74 dB and BW$ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW

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