A Robust Algorithm for the Design of Wideband Positive-Slope Linear Group Delay Filters
Author:
Affiliation:
1. Faculty of Electronic Engineering, University of Niš, Niš, Serbia
2. GEEPS, UMR CNRS, CentraleSupélec, Université Paris-Saclay, Gif-sur-Yvette, France
3. CentraleSupélec, Université Paris-Saclay, Gif-sur-Yvette, France
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/9904939/09803870.pdf?arnumber=9803870
Reference41 articles.
1. A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS
2. A Subthreshold Buffer-Based Biquadratic Cell and its Application to Biopotential Filter Design
3. A Compact Active Phaser with Enhanced Group Delay Linearity for Analog Signal Processing
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