Author:
Rafiq Ahsan,Chaudhry Shabbir Majeed,Awan Kamran Sadiq,Usman Muhammad
Cited by
5 articles.
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1. Design and implementation of low power and area efficient hybrid AHL multiplier;AIP Conference Proceedings;2024
2. FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells;JUCS - Journal of Universal Computer Science;2022-10-28
3. VLSI Implementation of Accuracy Configurable Radix-4 Adder for Digital Image Processing Applications;2022 1st IEEE International Conference on Industrial Electronics: Developments & Applications (ICIDeA);2022-10-15
4. Implementation of a Low-power N-bit Hybrid Carry Select Adder with Sum-Carry Selection;2022 IEEE International Conference on Data Science and Information System (ICDSIS);2022-07-29
5. RTL to GDSII Implementation of RADIX-4 Booth Multiplier;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28