Space Mapped Neuromodeling for Fast & Accurate Signal Integrity Analysis of Rough On-chip Copper Interconnects-Reference-Cited by-同舟云学术

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Space Mapped Neuromodeling for Fast & Accurate Signal Integrity Analysis of Rough On-chip Copper Interconnects

Published:2023-12-12 Issue: Volume: Page:1-3
ISSN:
Container-title:2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)
language:
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Author:

Kushwaha Suyash¹,Guglani Surila²,Soleimani Nastaran³,Pathania Sunil¹,Kumar Somesh⁴,Trinchero Riccardo³,Roy Sourajeet²,Sharma Rohit¹

Affiliation:

1. Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,India

2. Indian Institute of Technology Roorkee,Department of Electronics and Communication Engineering,Roorkee,India

3. Politecnico di Torino,Department of Electronics and Telecommunications,Torino,Italy

4. Indian Institute of Information Technology Gwalior,Department of Electronics and Communication Engineering,Gwalior,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10467193/10468066/10468464.pdf?arnumber=10468464

Reference12 articles.

1. Power comparison between high-speed electrical and optical interconnects for inter-chip communication

2. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

3. Effects of random rough surface on absorption by conductors at microwave frequencies

4. Multigigahertz Causal Transmission Line Modeling Methodology Using a 3-D Hemispherical Surface Roughness Approach

5. Developing a theoretical relationship between electrical resistivity, temperature, and film thickness for conductors

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